Our Location
Our Kelowna Design Center is located in the heart of the Okanagan Valley, a region known for its wineries, long hot summers and exceptional skiing. We offer the unique opportunity to design and develop highly integrated, mixed signal circuits for audio/video consumer electronics applications in one of the most beautiful locations in North America.
About ESS Technology
Our knowledge with signal converters has lead to some of the world’s best audio DACs and ADCs. This expertise along with a “hands-on” approach to all aspects of IC design, gives a working environment and quality of life that is second to none.
Main Duties
Design and develop high-performance mixed signal circuits utilizing advanced CMOS for the digital design portion of highly integrated, mixed signal integrated circuits developed for use in the ESS portfolio of products.
Responsible for performing the following duties in developing mixed signal circuits: specification definition, architecture, circuit design, layout supervision, and characterization of high-performance mixed signal circuits
Verify simulation, testing, qualifying and releasing designs to production
Support a team responsible for research, design, development and integrating the specifications and the architecture of new systems and new designs.
Employment Requirements
A Master in Electronic Engineering is required
10 years of experience in analog design
Strong track Set of Analog IC design
Strong Proficiency with Spice/Spectre, MATLAB and PSSPNoise simulations.
Working knowledge of various circuits including linear voltage regulators, switching voltage regulators, data converters, op-amps, bandgap circuits, transceivers, active filters, and PLL design blocks just to name a few.
Strong expertise in CMOS technologies (0.15-um and down) containing large digital blocks and precision analog circuits.
Able to work and interact with analog engineers to deliver mixed signal solutions.
Strong set of Analog IC design skills in a wide range of circuits. Strong layout knowledge and parasitic component understanding is a must.
Expertise with software tools such as schematic entry, SPICE, Matlab, etc. is required.
Process and device physics knowledge is a strong plus. Basic digital design skills at the gate level and utilizing Verilog is an added benefit.
Be comfortable with common lab tools, such as oscilloscopes, function generators, power supplies and soldering equipment.
Specific Skills Required
Recognition of amplifier configurations at the block level: instant grasp of noise gain, signal gain and so forth.
To be able to look at an op-amp drawing and describe the pole zero locations, know what product of what resistors and capacitors are creating the poles and zeros. Understand Open-Loop Characteristics, identify Phase Margin on a Bode plot, know how phase margin varies with closed loop gain.
Comprehend 1/f noise and its relation to gate area. Know that the noise of bipolar devices is re/2 and for a FET 2/3gm. Describe shot noise as distinct from voltage noise and explain its origin. Understand why input stage noise should dominate, optimize load networks for low noise.
Comprehend, at the device level, dominant pole compensation and correctly identify the Gm and C that determine its value. Understand zero compensation techniques and its impact on excess phase.
Know the limitations of R-2R networks, on-resistance errors etc. Correctly draw a R-2R network in both Voltage Mode and Current mode.
Understand the first principles of Sigma-Delta modulation and correctly derive the STF and NTF for a block-diagram level Sigma-Delta modulator.
Understand staticizer failure (meta-stability) and outline techniques to reduce it.
Understand that a PLL is a second order system and what that means to the zero in the loop filter. Point out the optimum point for phase noise given a poor low frequency local oscillator and a good quality input clock. Know what a variable modulus pre-scalar does. Accurately describe what phase noise is, and how it scales with frequency,
Understand the principle of a band-gap circuit and know the acronyms PTAT and ITAT, show a simple continuous time band-gap. Never having a seen a switch-cap band-gap nevertheless be able to identify the PTAT and ITAT aspect.
Draw at least one implementation of a bi-quad stage of a filter, know why all filters are reducible to bi-quads.. Understand what Q is, and the optimum placement of w,Q in a bi-quad chain for signal level issues.
Explain why an RF signal is matched at the receiver and show an outline of how this is commonly achieved at the devices level.
Draw schematics with ease, those drawing corresponding to signal from left to right (or rarely, visa-versa) and always with higher voltages at the top.
Benefits
ESS Technology, Inc. offers MSP-BC, Extended Health Care, Dental, Vision, Life, AD&D and Life Term benefits.
Salary range: $90,000 to $120,000 per year
TO APPLY:
Please submit your Resume to hr@esstech.com